Typical prior art semiconductor memory cells have only two stable states for storing complementary bit levels. In a first of the states the cell stores a binary zero level, and in a second of the states the cell stores a binary one level. The cell typically includes first and second output terminals such that when the cell stores a binary zero level the cell respectively supplies low and high voltages to the first and second tenninals; when the cell stores a binary one level the cell respectively supplies high and low voltages to the first and second output terminals. The typical cell also includes first and second signal input tenninals responsive to complementary bi-level voltages such that when a binary zero level is written into the cell, low and high voltages are respectively applied to the first and second input terminals; when a binary one level is written into the cell the first and second input terminals are respectively responsive to high and low voltage levels.
The typical prior art semiconductor memory cell includes first and second inverters connected to each other in a back-to-back regenerative feedback arrangement. Each of the inverters has an input and output terminal such that the output terminal of the first inverter is connected to the input terminal of the second inverter and the output terminal of the second inverter is connected to the input terminal of the first inverter. In essence, the output terminals of the first and second inverters are the first and second output terminals of the cell from which the binary state of the cell is read during a read operation. The voltage levels at the first and second input terminals are respectively supplied to input terminals of first and second write lines or leads via gates that are open during a write operation. In the typical integrated circuit semiconductor memory, the gates are referred to as pass gates, each formed by a source drain path of a field effect transistor (FET) having a gate electrode responsive to a write pulse source. The voltage levels at the cell first and second output terminals are supplied to first and second data lines or leads that are coupled to a read logic network on an integrated chip including the memory cells.
A substantial amount of the area of each cell is occupied by the write and data lines. The write and data lines occupy a considerably greater area of each cell than the active elements, i.e., field effect transistors (FETs), forming the inverters of each cell. To maximize packing density of each cell on the integrated circuit chip, it is desirable to maximize the use of the write and data lines of each memory cell.